1. Field of the Invention
This invention is related to computer circuitry, in general, and to a floating point processor which performs a subtraction function, in particular.
2. Prior Art
There are many computer circuits and systems which are known in the art. These computer circuits and systems are used in many applications in the modern day world. Computers of more recent vintage are, of course, much faster, much smaller and much more powerful in operation. In order to achieve all of these attributes, continuing investigation of smaller, faster circuitry is underway. In order to make computers both smaller and faster, it is desirable to reduce the size of various words or numbers so that operations thereon can be expedited. That is, if a word can be made one bit shorter (while maintaining the same content or accuracy), an element in virtually every device in the data path can be saved also. Consequently, it is desirable to achieve system operation with minimal additions or modifications to existing equipment and, as well, word or number construction therein.
One operation and pertinent circuit used in many computers is a floating point processor which operates on floating point numbers. To perform a floating point number subtraction, the number with the smaller exponent has to be denormalized before the subtraction can take place. This is carried out by shifting the mantissa portion of the smaller number to the right by the number of places equal to the difference between the exponents of the numbers. The number is renormalized after the subtraction.
In order to keep the error of the subtraction less than or equal to 1/2 LSB, some extra storage must be provided to store the bits of data shifted out to the right during the denormalization procedure. These bits also have to participate in the subtraction. The number of these bits, called "guard bits", is usually three or more. It can be shown that, without using special hardware circuitry and doing a subtraction as described above, the error bound will typically be: EQU (1/2)*(1+2.sup.(-g+2)) LSB
where g is the number of guard bits. In the past, this error bound has been kept close to 1/2 LSB by adding more guard bits. However, this means added hardware along the whole data path. Moreover, this approach is undesirable because the best error bound (1/2 LSB) is still not attained, causing the result of arithmetic calculations to be less than predictable.
It is highly desirable to be able to maintain the error to less than 1/2 LSB while maintaining a minimum hardware configuration.